The present invention relates generally to semiconductor devices, and more particularly to power MOSFET devices.
Power MOSFET devices are employed in applications such as automobile electrical systems, power supplies, and power management applications. Such devices should sustain high voltage in the off-state and supply high current with a low voltage drop in the on-state.
FIG. 1 illustrates a typical structure for an N-channel power MOSFET. An N-epitaxial silicon layer 1 formed over an N+ silicon substrate 2 contains p-body regions 5a and 6a, and N+ source regions 7 and 8 for two MOSFET cells in the device. P-body regions 5 and 6 may also include deep p-body regions 5b and 6b. A source-body electrode 12 extends across certain surface portions of epitaxial layer 1 to contact the source and body regions. The N-type drain for both cells is formed by the portion of N-epitaxial layer 1 extending to the upper semiconductor surface in FIG. 1. A drain electrode (not separately shown) is provided at the bottom of N+ substrate 2. An insulated gate electrode 18 comprising a dielectric such as silicon dioxide and polysilicon lies over portions of the source and body regions and the surface of the drain region between the body regions.
The on-resistance of the conventional MOSFET shown in FIG. 1 is determined largely by the drift zone resistance in epitaxial layer 1. The drift zone resistance is in turn determined by the doping and the layer thickness of epitaxial layer 1. However, to increase the breakdown voltage of the device, the doping concentration of epitaxial layer 1 must be reduced while the layer thickness is increased. Curve 20 in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage for a conventional MOSFET. Unfortunately, as curve 20 shows, the on-resistance of the device increases rapidly as its breakdown voltage increases. This rapid increase in resistance presents a problem when the MOSFET is to be operated at higher voltages, particularly at voltages greater than a few hundred volts.
FIG. 3 shows a MOSFET that is designed to operate at higher voltages with a reduced on-resistance. This MOSFET is disclosed in paper No. 26.2 in the Proceedings of the IEDM, 1998, p. 683. This MOSFET is similar to the conventional MOSFET shown in FIG. 2 except that it includes p-type doped regions 40 and 42 which extend from beneath the body regions 5 and 6 into to the drift region of the device. The p-type doped regions 40 and 42 define columns in the drift region that are separated by n-type doped columns, which are defined by the portions of the epitaxial layer 1 adjacent the p-doped regions 40 and 42. The alternating columns of opposite doping type cause the reverse voltage to be built up not only in the vertical direction, as in a conventional MOSFET, but in the horizontal direction as well. As a result, this device can achieve the same reverse voltage as in the conventional device with a reduced layer thickness of epitaxial layer 1 and with increased doping concentration in the drift zone. Curve 25 in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage of the MOSFET shown in FIG 3. Clearly, at higher operating voltages, the on-resistance of this device is substantially reduced relative to the device shown in FIG. 1, essentially increasing linearly with the breakdown voltage.
The improved operating characteristics of the device shown in FIG. 3 are based on charge compensation in the drift region of the transistor. That is, the doping in the drift region is substantially increased, e.g., by an order of magnitude or more, and the additional charge is counterbalanced by the addition of columns of opposite doping type. The blocking voltage of the transistor thus remains unaltered. The opposite doping type charge compensating columns do not contribute to the current conduction when the device is in its on state. These desirable properties of the transistor depend critically on the degree of charge compensation that is achieved between adjacent columns of opposite doping type. Unfortunately, nonuniformities in the dopant gradient of the columns can be difficult to avoid as a result of limitations in the control of process parameters during their fabrication. For example, diffusion across the interface between the columns and the substrate and the interface between the columns and the p-body region will give rise to changes in the dopant concentration of the portions of the columns near those interfaces.
The structure shown in FIG. 3 can be fabricated with a process sequence that includes multiple epitaxial deposition steps, each followed by the introduction of the appropriate dopant. Unfortunately, epitaxial deposition steps are expensive to perform and thus this structure is expensive to manufacture.
Accordingly, it would be desirable to provide a method of fabricating the MOSFET structure shown in FIG. 3 that requires a minimum number of epitaxial deposition steps so that it can be produced less expensively while also allowing sufficient control of process parameters so that a high degree of charge compensation can be achieved in adjacent columns of opposite doping type in the drift region of the device.
In accordance with the present invention, a power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a thin oxide layer and a polycrystalline semiconductor material (e.g., polysilicon) that includes a dopant of the second conductivity type. The thin oxide layer is dissolved into the epitaxial layer, dopant is diffused from the trenches into portions of the epitaxial layer adjacent to the trenches, and the polycrystalline semiconductor material is converted to a single crystal material, thus forming the p-type doped regions that cause the reverse voltage to be built up in the horizontal direction as well as the vertical direction.
In accordance with another aspect of the invention, a method is provided for forming a power MOSFET. The method begins by providing a substrate of a first conductivity type and depositing an epitaxial layer on the substrate. The epitaxial layer has a first conductivity type. First and second body regions are formed in the epitaxial layer to define a drift region therebetween. The body regions have a second conductivity type. First and second source regions of the first conductivity type are formed in the first and second body regions, respectively. A plurality of trenches are formed in the drift region of the epitaxial layer. A material having a dopant of the second conductivity type is epitaxially deposited in the trenches. The trenches extend toward the substrate from the first and second body regions. A layer of silicon dioxide is formed on the walls and the bottom of the trenches. Polycrystalline semiconductor material having a dopant of the second conductivity type is deposited in the trenches. The layer of silicon dioxide is dissolved into the epitaxial layer by heating. At least a portion of the dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches and the polycrystalline semiconductor material is converted to single crystal material